VHDL component output returns zeros -

i'm writing in vhdl essay , i'm facing strange situation. i've written components, simulated , tested them, , seems works fine. however, when simulating top entity, i'm getting zeros result! please take @ following listings:

top entity:

library ieee; use ieee.std_logic_1164.all;  entity foobar   port ( data_i : in std_logic_vector(39 downto 0);              sum_12bit_o : out std_logic_vector(11 downto 0)             ); end foobar;  architecture behavioral of foobar  --declare components component four_10bit_word_adder     port( --input signals             a_byte_in: in std_logic_vector(9 downto 0);             b_byte_in: in std_logic_vector(9 downto 0);             c_byte_in: in std_logic_vector(9 downto 0);             d_byte_in: in std_logic_vector(9 downto 0);             cin: in std_logic;             --output signals             val12bit_out: out std_logic_vector(11 downto 0)     ); end component;  -- signal declaration signal int: std_logic_vector(11 downto 0); signal intdata: std_logic_vector(39 downto 0);  begin     intdata <= data_i; --debug         u1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),                                                          intdata(19 downto 10), intdata(9 downto 0),                                                '0', int);  end behavioral; 

four_10bit_word_adder:

library ieee; use ieee.std_logic_1164.all;  entity four_10bit_word_adder  generic (     bits: integer := 10   );  port( --input signals         a_byte_in: in std_logic_vector(bits-1 downto 0);         b_byte_in: in std_logic_vector(bits-1 downto 0);         c_byte_in: in std_logic_vector(bits-1 downto 0);         d_byte_in: in std_logic_vector(bits-1 downto 0);         cin: in std_logic;         --output signals         val12bit_out: out std_logic_vector(bits+1 downto 0) );  end four_10bit_word_adder;  architecture behavioral of four_10bit_word_adder  -- component declaration  component compressor_4_2     port(a,b,c,d,cin : in std_logic;            cout, sum, carry : out std_logic           ); end component;  --------------------------------------------------------+ component generic_11bit_adder port (     a:  in  std_logic_vector(10 downto 0); --input     b:  in  std_logic_vector(10 downto 0); --input b     ci: in  std_logic;                           --carry in     o:  out std_logic_vector(10 downto 0); --sum     co: out std_logic                            --carry out   ); end component; --------------------------------------------------------+  -- declare internal signals signal int: std_logic_vector(bits-1 downto 0); -- int(8) final cout signal signal byte_out: std_logic_vector(bits-1 downto 0); signal carry: std_logic_vector(bits-1 downto 0); signal int11bit: std_logic_vector(bits downto 0); -- following signals necessary produce concatenated inputs 10-bit adder. -- see paper more info.  signal concat_a: std_logic_vector(bits downto 0); signal concat_b: std_logic_vector(bits downto 0); signal co : std_logic;  begin      a0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),                                  c_byte_in(0), d_byte_in(0),                                 '0', int(0), byte_out(0), carry(0));     instances: in 1 bits-1 generate         a: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),                                               c_byte_in(i), d_byte_in(i), int(i-1),                                              int(i), byte_out(i), carry(i));     end generate;      r9: generic_11bit_adder port map (concat_a, concat_b, '0', int11bit, co);  concat_a <= int(8) & byte_out; concat_b <= carry & '0';  process (co) begin     if (co = '1')          val12bit_out <= '1' & int11bit;     else         val12bit_out <= '0' & int11bit;     end if;  end process; end behavioral; 

4:2 compressor

library ieee; use ieee.std_logic_1164.all;  entity compressor_4_2      port(a,b,c,d,cin : in std_logic;            cout, sum, carry : out std_logic );  end compressor_4_2;  architecture behavioral of compressor_4_2  -- internal signal definitions signal stage_1: std_logic;  begin  stage_1 <= d xor (b xor c); cout <= not((b nand c) , (b nand d) , (c nand d)); sum <= (a xor cin) xor stage_1; carry <= not((a nand cin) , (stage_1 nand cin) , (a nand stage_1));  end behavioral; 

generic 11-bit adder:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity generic_11bit_adder   generic (     bits: integer := 11   );   port (     a:  in  std_logic_vector(bits-1 downto 0);     b:  in  std_logic_vector(bits-1 downto 0);     ci: in  std_logic;     o:  out std_logic_vector(bits-1 downto 0);     co: out std_logic   ); end entity generic_11bit_adder;  architecture behavioral of generic_11bit_adder begin  process(a,b,ci)    variable sum:         integer;    -- note: have 1 bit more store carry out value.   variable sum_vector:  std_logic_vector(bits downto 0);   begin    -- compute our integral sum, converting operands integers.    sum := conv_integer(a) + conv_integer(b) + conv_integer(ci);    -- now, convert integral sum std_logic_vector, of size bits+1    sum_vector := conv_std_logic_vector(sum, bits+1);    -- assign outputs   o <= sum_vector(bits-1 downto 0);    co <=  sum_vector(bits); -- carry significant bit  end process;  end behavioral; 

i've tried ton of things, without success. have idea doing wrong? sorry long question , thank time.

take @ process generate val12bit_out in four_10bit_word_adder entity. it's missing input.

also, there several other issues. fixing 1 issue not fix everything. once fix it, think things lot more clear.