Error Number 10170 in Verilog using If/Else and Case Statements -

i trying compile following code whenever errors:

'10170 verilog hdl syntax error @ fsm.v(9) near text "case"; expecting operand'

'10170 verilog hdl syntax error @ fsm.v(9) near text ")"; epecting "<=" or "="'

'10170 verilog hdl syntax error @ fsm.v(11) near text "4"; expecting "end"'

module fsm (in0, in1, in2, in3, s, out0, out1, out2, out3);  input in0, in1, in2, in3, s; output out0, out1, out2, out3; reg out0, out1, out2, out3; @(in0 or in1 or in2 or in3 or s) begin     if(s == 0) begin     {         case({in3, in2, in1, in0})             4'b0000: {out3, out2, out1, out0} = 4'b0000; //0->0             4'b0001: {out3, out2, out1, out0} = 4'b0011; //1->3             4'b0010: {out3, out2, out1, out0} = 4'b0110; //2->6             4'b0011: {out3, out2, out1, out0} = 4'b1001; //3->9             4'b0100: {out3, out2, out1, out0} = 4'b0010; //4->2             4'b0101: {out3, out2, out1, out0} = 4'b0101; //5->5             4'b0110: {out3, out2, out1, out0} = 4'b1000; //6->8             4'b0111: {out3, out2, out1, out0} = 4'b0001; //7->1             4'b1000: {out3, out2, out1, out0} = 4'b0100; //8->4             4'b1001: {out3, out2, out1, out0} = 4'b0111; //9->7         endcase     }     end     else begin     {         case({in3, in2, in1, in0})             4'b0000: {out3, out2, out1, out0} = 4'b0111; //0->7             4'b0001: {out3, out2, out1, out0} = 4'b1000; //1->8             4'b0010: {out3, out2, out1, out0} = 4'b1001; //2->9             4'b0011: {out3, out2, out1, out0} = 4'b0000; //3->0             4'b0100: {out3, out2, out1, out0} = 4'b0001; //4->1             4'b0101: {out3, out2, out1, out0} = 4'b0010; //5->2             4'b0110: {out3, out2, out1, out0} = 4'b0011; //6->3             4'b0111: {out3, out2, out1, out0} = 4'b0100; //7->4             4'b1000: {out3, out2, out1, out0} = 4'b0101; //8->5             4'b1001: {out3, out2, out1, out0} = 4'b0110; //9->6         endcase     }     end end endmodule 

with last error repeating every line of code that's found in case statements. if has idea of have wrong , how fix i'd appreciate it!

remove curly braces ({..}) after if condition. verilog not c requires curly braces, in verilog, use begin..end multi-line procedural statements.

also, use of always @(*) (or always_comb in systemverilog) recommended automatic sensitivity, instead of manual sensitivity of always @(in0 or in1 or in2 or in3 or s).

you might have go through detailed verilog syntax. refer begin..end link , always sensitivity question of information. refer ieee 1364-2001 verilog , ieee 1800-2012 systemverilog.