variable assignment - Verilog: Assigning a register to a register -

in below verilog assignment register rotationdoner assigned signal , other register rotationdonerr assigned same register. doesn't mean both registers hold same value , condition never true?

input wire rotationdone; // module definition  reg rotationdoner; reg rotationdonerr;  rotationdoner <= rotationdone;  rotationdonerr <= rotationdoner;    if ( rotationdoner && (! rotationdonerr ) ) begin      interrupttocpu <= 1;  end  

thanks clarification!

i assume there procedural block based on edge of clocking event in code.

when have non blocking assignments (<=), evaluation of rhs takes place in active event region, while lhs updated in nba region.

consider following example, non-blocking assignments evaluates rhs in active region , stores value internally, temporarily same time stamp (the older value of a stored internally here). in nba region, lhs updated (b gets older value of a , a gets value of inp).

// synthesize simple wire = inp; b = a;  // synthesize shift register <= inp; b <= a; 

similarly, here rotationdonerr flop-ed version of rotationdoner. since, on clock edge, rotationdoner loaded rotationdone , @ same time, rotationdonerr loaded rotationdoner.

so, if condition evaluates true whenever: current input value true (current input rotationdone = 1'b1) and negated previous value of input (previous input rotationdone = 1'b0) satisfied.

refer non-blocking assignments link , many other pdfs on net, including cummingssnug2000sj_nba_rev1_2 paper more information.