Encoder VHDL Code -

-- code design here  library ieee;  use ieee.std_logic_1164.all;  entity encoder8_3       port(           din : in std_logic_vector(7 downto 0);           dout : out integer range 0 15           );  end encoder8_3;  architecture encoder8_3_arc of encoder8_3  begin      dout <= "0" when (din="10000000") else             "1" when (din="01000000") else             "2" when (din="00100000") else             "3" when (din="00010000") else             "4" when (din="00001000") else             "5" when (din="00000100") else             "6" when (din="00000010") else             "7";  end encoder8_3_arc; 

will code run?i want return integers in place of binary equivalent.

why won't code compile?

because integer literals in vhdl not have quotes:

library ieee;  use ieee.std_logic_1164.all;  entity encoder8_3       port(           din : in std_logic_vector(7 downto 0);           dout : out integer range 0 15           );  end encoder8_3;  architecture encoder8_3_arc of encoder8_3  begin      dout <= 0 when (din="10000000") else             1 when (din="01000000") else             2 when (din="00100000") else             3 when (din="00010000") else             4 when (din="00001000") else             5 when (din="00000100") else             6 when (din="00000010") else             7;  end encoder8_3_arc; 

http://www.edaplayground.com/x/5f2m